Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs

TL;DR

This paper introduces an interconnect-aware logic resynthesis technique for multi-die FPGAs that reduces super-long inter-die lines, thereby improving critical path delay and physical design flexibility.

Contribution

It proposes a novel logic resynthesis method utilizing die partitioning to minimize inter-die connections before physical implementation.

Findings

Reduces super-long lines by up to 24.8% in 2-die FPGAs.

Achieves an average of 1.65% reduction in inter-die connections on MCNC benchmarks.

Improves physical design flexibility and critical path delay in multi-die FPGA designs.

Abstract

Multi-die FPGAs enable device scaling beyond reticle limits but introduce severe interconnect overhead across die boundaries. Inter-die connections, commonly referred to as super-long lines (SLLs), incur high delay and consume scarce interposer interconnect resources, often dominating critical paths and complicating physical design. To address this, this work proposes an interconnect-aware logic resynthesis method that restructures the LUT-level netlist to reduce the number of SLLs. The resynthesis engine uses die partitioning information to apply logic resubstitutions, which simplifies local circuit structures and eliminates SLLs. By reducing the number of SLLs early in the design flow, prior to physical implementation, the proposed method shortens critical paths, alleviates pressure on scarce interposer interconnect resources, and improves overall physical design flexibility. We further build a tool flow for multi-die FPGAs by integrating the proposed resynthesis method with packing and placement. Experimental results on the EPFL benchmarks show that, compared with a state-of-the-art framework, the proposed method reduces the number of SLLs by up to 24.8% for a 2-die FPGA and up to 27.38% for a 3-die FPGA. On MCNC benchmarks, our tool flow achieves an average SLL reduction of 1.65% while preserving placement quality. On Koios benchmarks, where fewer removable SLLs exist, several designs still exhibit considerable inter-die edge reductions. Overall, the results confirm that reducing inter-die connections at the logic level is an effective approach for multi-die FPGAs.