Hardware-Aware Design of a GNN-Based Hit Filtering Algorithm for the Belle II Level-1 Trigger

TL;DR

This paper presents a hardware-aware model compression workflow for a GNN-based hit filtering algorithm, enabling efficient FPGA deployment in the Belle II trigger system while maintaining high performance.

Contribution

It introduces a novel model compression approach tailored for FPGA deployment of GNNs in high-energy physics trigger systems, optimizing for hardware constraints.

Findings

Over two orders of magnitude reduction in computational cost.

Maintained high hit efficiency and background rejection.

Minimal decrease in AUC score from 97.4 to 96.8.

Abstract

The Belle~II experiment operates at high luminosity, where an increasing beam-induced background imposes stringent demands on the hardware Level-1 trigger system, which must operate under tight latency and bandwidth constraints. To achieve online data reduction within the Level-1 trigger system, we have developed a hit-filtering algorithm based on the lightweight Interaction Network architecture. In this work, we present a hardware-aware model-compression workflow for this hit-filtering algorithm targeting deployment on FPGA devices within the Belle~II trigger system. The network is adapted to the detector and trigger conditions through model-size and graph-size reduction, low-precision (4 bit) fixed-point arithmetic, and unstructured pruning. We assess the resulting design using the total number of bit operations as a hardware-aware computational complexity metric. Using this metric, we identify a configuration that decreases this cost by more than two orders of magnitude relative to the full-precision reference implementation. This reduction is achieved while preserving performance close to the reference model in terms of hit efficiency and background rejection, as indicated by only a modest decrease in the AUC score from 97.4 to 96.8, evaluated on Belle~II collision data.