Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA
Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut, Hiroshi Nakano, Manon Dampfhoffer, Thomas Mesquida, Hiroaki Nishi, Thomas Dalgaty, Tomasz Kryjak

TL;DR
This paper presents a hardware-efficient FPGA implementation of event-graph neural networks for neuromorphic audio classification and keyword spotting, achieving high accuracy with low latency and power consumption.
Contribution
It introduces a novel FPGA-based event-graph neural network architecture for audio processing, including the first hardware-accelerated evaluation for SSC and end-to-end FPGA keyword spotting.
Findings
92.7% accuracy on SHD dataset, close to state-of-the-art
First hardware-accelerated evaluation for SSC
End-to-end FPGA keyword spotting with 95% accuracy, 10.53μs latency
Abstract
As the volume of data recorded by embedded edge sensors increases, particularly from neuromorphic devices producing discrete event streams, there is a growing need for hardware-aware neural architectures that enable efficient, low-latency, and energy-conscious local processing. We present an FPGA implementation of event-graph neural networks for audio processing. We utilise an artificial cochlea that converts time-series signals into sparse event data, reducing memory and computation costs. Our architecture was implemented on a SoC FPGA and evaluated on two open-source datasets. For classification task, our baseline floating-point model achieves 92.7% accuracy on SHD dataset - only 2.4% below the state of the art - while requiring over 10x and 67x fewer parameters. On SSC, our models achieve 66.9-71.0% accuracy. Compared to FPGA-based spiking neural networks, our quantised model reaches…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neural Networks and Reservoir Computing
