Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture

TL;DR

This paper introduces an FPGA-based p-bit annealer architecture that efficiently supports fully connected Ising models, significantly reducing energy and resource consumption for large-scale stochastic optimization tasks.

Contribution

It proposes a novel dual-BRAM delay-line architecture combined with a spin-serial and replica-parallel update schedule to enhance scalability and reduce memory overhead in p-bit-based annealers.

Findings

Successfully solves an 800-node MAX-CUT problem.

Achieves up to 50% energy reduction.

Reduces logic resource usage by over 90%.

Abstract

Probabilistic bits (p-bits) offer an energy-efficient hardware abstraction for stochastic optimization; however, existing p-bit-based simulated annealing accelerators suffer from poor scalability and limited support for fully connected graphs due to fan-out and memory overhead. This paper presents an energy-efficient FPGA architecture for stochastic simulated quantum annealing (SSQA) that addresses these challenges. The proposed design combines a spin-serial and replica-parallel update schedule with a dual-BRAM delay-line architecture, enabling scalable support for fully connected Ising models while eliminating fan-out growth in logic resources. By exploiting SSQA, the architecture achieves fast convergence using only final replica states, significantly reducing memory requirements compared to conventional p-bit-based annealers. Implemented on a Xilinx ZC706 FPGA, the proposed system solves an 800-node MAX-CUT benchmark and achieves up to 50% reduction in energy consumption and over 90\% reduction in logic resources compared with prior FPGA-based p-bit annealing architectures. These results demonstrate the practicality of quantum-inspired, p-bit-based annealing hardware for large-scale combinatorial optimization under strict energy and resource constraints.