Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware

TL;DR

This paper presents a flexible design environment for real-time few-shot learning on edge FPGA hardware, enabling arbitrary bit-widths and improved throughput without accuracy loss.

Contribution

It introduces a methodology using the FINN framework with customizations to support arbitrary fixed-point bit-widths for FPGA-based few-shot learning.

Findings

Achieved approximately twice the throughput compared to conventional fixed-point implementations.

Maintained accuracy while reducing bit-widths through specific optimizations.

Demonstrated effectiveness on CIFAR-10 dataset.

Abstract

In this study, we propose an implementation methodology of real-time few-shot learning on tiny FPGA SoCs such as the PYNQ-Z1 board with arbitrary fixed-point bit-widths. Tensil-based conventional design environments limited hardware implementations to fixed-point bit-widths of 16 or 32 bits. To address this, we adopt the FINN framework, enabling implementations with arbitrary bit-widths. Several customizations and minor adjustments are made, including: 1.Optimization of Transpose nodes to resolve data format mismatches, 2.Addition of handling for converting the final reduce mean operation to Global Average Pooling (GAP). These adjustments allow us to reduce the bit-width while maintaining the same accuracy as the conventional realization, and achieve approximately twice the throughput in evaluations using CIFAR-10 dataset.