Real-time graph neural networks on FPGAs for the Belle II electromagnetic calorimeter

TL;DR

This paper demonstrates a real-time FPGA implementation of a Graph Neural Network for the Belle II experiment's calorimeter, improving cluster resolution and background suppression within strict latency constraints.

Contribution

It introduces the first FPGA-based GNN system integrated into a collider's real-time trigger, enhancing clustering and classification performance.

Findings

Energy resolution comparable to baseline trigger

Position resolution improved by up to 18% in central regions

Cluster purity and efficiency increased significantly

Abstract

We present the development and evaluation of a real-time Graph Neural Network-based trigger for the electromagnetic calorimeter of the Belle II experiment at the SuperKEKB collider. The algorithm processes calorimeter trigger cells as graph nodes to perform clustering, feature extraction, and per-cluster signal classification with deterministic latency compatible with the first-level trigger readout system. The model predicts cluster positions and energies and provides a signal classification score, enabling a more flexible clustering strategy than the baseline trigger algorithm. Implemented on an FPGA and integrated into the Belle II trigger chain for synchronous operation, the system sustains the 8 MHz trigger throughput with an end-to-end latency of 3.168 $\mu$s. The performance is evaluated using simulated events and collision data. The energy resolution is comparable to the baseline trigger, while the position resolution for high-energy clusters improves by up to 18 percent in the central detector region. Cluster purity increases by up to 20 percent at low energies for isolated clusters, and cluster efficiency improves by up to 20 percent for overlapping clusters. The signal classifier enables additional background suppression at fixed signal retention. These results demonstrate the first operation of a Graph Neural Network-based reconstruction system implemented on FPGAs within the real-time trigger readout path of a collider experiment.