Mixed precision solvers with half-precision floating point numbers for Lattice QCD on A64FX processor

TL;DR

This paper explores the practicality of using half-precision floating-point numbers in mixed-precision solvers for lattice QCD on A64FX processors, demonstrating improved stability with rescaling techniques.

Contribution

It introduces rescaling steps in mixed-precision solvers to enhance stability and demonstrates their effectiveness in lattice QCD simulations on A64FX processors.

Findings

FP16-based solver shows improved stability.

Additional iteration count within 20% of FP64 version.

Rescaling methods prevent numerical underflows.

Abstract

We investigate the use of half-precision floating-point numbers (FP16) in mixed-precision linear solvers for lattice QCD simulations. Since the emergence of GPUs for general-purpose, mixed-precision algorithms that combine single-precision (FP32) with double-precision (FP64) arithmetics have become widely used in this field and others. While FP32-based methods are now well established, we examine the practicality of using FP16. In this work, we introduce rescaling steps in both the outer iterative refinement step and the inner BiCGStab solver to avoid numerical instability. In our experiments with a simple Wilson kernel, the solver shows improved stability, and the additional iteration count compared to the FP64 version remains within 20\%, indicating that the FP16 version is practical for use. We believe that the proposed rescaling methods can also benefit other mixed precision preconditioners in avoiding underflows.