Implementation and Performance Evaluation of CMOS-integrated Memristor-driven Flip-flop Circuits
Paras Tiwari, Narendra Singh Dhakad, Shalu Rani, Sanjay Kumar, Themis Prodromakis

TL;DR
This paper presents the implementation and evaluation of memristor-driven logic gates and flip-flops integrated with CMOS technology, demonstrating significant improvements in area, power, and delay over existing designs.
Contribution
It introduces optimized memristor-driven logic and sequential circuits in CMOS, with experimental validation and a comprehensive performance comparison to state-of-the-art work.
Findings
Performance metrics reduced by over 24% in area, 60% in power, and 58% in delay.
Experimental validation shows low variability in memristor switching.
Design achieves low-power, low-cost, ultrafast, and compact circuits.
Abstract
In this work, we report implementation and performance evaluation of memristor-driven fundamental logic gates, including NOT, AND, NAND, OR, NOR, and XOR, and novel and optimized design of the sequential logic circuits, such as D flip-flop, T-flip-flop, JK-flip-flop, and SR-flip-flop. The design, implementation, and optimization of these logic circuits were performed in SPECTRE in Cadence Virtuoso and integrated with 90 nm CMOS technology node. Additionally, we discuss an optimized design of memristor-driven logic gates and sequential logic circuits, and draw a comparative analysis with the other reported state-of-the-art work on sequential circuits. Moreover, the utilized memristor framework was experimentally pre-validated with the experimental data of Y2O3-based memristive devices, which shows significantly low values of variability during switching in both device-to-device (D2D) and…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Low-power high-performance VLSI design · Ferroelectric and Negative Capacitance Devices
