Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories

TL;DR

This paper presents a co-designed device-circuit interface for AFMTJ memories that enhances reliability and performance by addressing ultrafast dynamics and low TMR challenges through novel drivers and sensing circuits.

Contribution

It introduces an asymmetric pulse driver and a self-timed sense amplifier tailored for AFMTJ characteristics, improving robustness and efficiency.

Findings

Achieves deterministic picosecond switching with the proposed driver.

Maintains AFMTJ latency and energy advantages under realistic conditions.

Outperforms standard MRAM interfaces in robustness and yield.

Abstract

Antiferromagnetic Tunnel Junctions (AFMTJs) offer picosecond switching and high integration density for in-memory computing, but their ultrafast dynamics and low tunnel magnetoresistance (TMR) make state-of-the-art MRAM interfaces unreliable. This work develops a device-circuit co-designed read/write interface optimized for AFMTJ behavior. Using a calibrated SPICE AFMTJ model as a baseline, we identify the limitations of conventional drivers and propose an asymmetric pulse driver (PD) for deterministic picosecond switching and a self-timed sense amplifier (STSA) with dynamic trip-point tuning for low-TMR sensing. Our experiments using SPICE and Monte Carlo evaluations demonstrate that the proposed circuits preserve AFMTJ latency and energy benefits while achieving robust read/write yield under realistic PVT and 3D integration parasitics, outperforming standard MRAM front-ends under the same conditions.