Fermilab PIP II machine protection system digitized data noise elimination scheme and its FPGA implementation

TL;DR

This paper presents a novel FPGA-based digital noise suppression scheme for Fermilab's PIP-II machine protection system, effectively reducing 60 Hz and high-frequency noise in beam loss signals for improved detection accuracy.

Contribution

It introduces a new real-time digital filtering approach with specialized FPGA blocks for noise suppression in beam loss monitoring systems, enhancing signal integrity.

Findings

Successfully implemented on FPGA with expected performance

Effective suppression of 60 Hz and high-frequency noise

Improved beam loss detection accuracy

Abstract

In Fermilab's PIP-II machine protection system, beam loss signals from various detectors are digitized at 125 MS/s. Noise from both high-frequency sources and low-frequency 60 Hz AC power equipment can contaminate the data. To suppress noise across these ranges especially 60 Hz and its harmonics, which overlap with beam loss signal frequencies advanced digital processing beyond standard filtering is required. Several real-time functional blocks were simulated and tested on an FPGA: (1) a dual time-constant discharging integrator filter, (2) a de-ripple baseline extraction and storage block, and (3) a fast-recovery discharging integrator. The nonlinear IIR integrator filter removes high-frequency noise and feeds into the baseline extractor. Upon detecting abrupt beam loss, it switches to a longer time constant to prevent baseline distortion. The de-ripple block calculates a valid baseline by averaging over multiple 60 Hz periods, storing results in a 4096-word FPGA RAM. This baseline is subtracted from raw data before integration by the fast-recovery block, which resets quickly after use. All blocks achieved expected performance.