Fault Tolerant Design of IGZO-based Binary Search ADCs

TL;DR

This paper introduces a hierarchical fault injection framework to analyze and improve the defect tolerance of IGZO-based Binary Search ADCs, significantly enhancing fault coverage with minimal area and power overhead.

Contribution

It develops a combined transistor-level and system-level fault analysis method for IGZO ADCs, enabling targeted redundancy and improved defect tolerance.

Findings

Fault coverage increased from 60% to 92% for single faults.

Fault coverage increased from 34% to 77.6% for multi-fault scenarios.

Achieved these improvements with only 4.2% area and 6% power overhead.

Abstract

Thin-film technologies such as Indium Gallium Zinc Oxide (IGZO) enable Flexible Electronics (FE) for emerging applications in wearable sensing, personal health monitoring, and large-area systems. Analog-to-digital converters (ADCs) serve as critical sensor interfaces in these systems. Yet, their vulnerability to manufacturing defects remains poorly understood despite unipolar technologies' inherently high defect densities and process variations compared to mature CMOS technologies. We present a hierarchical fault injection framework to characterize defect sensitivity in Binary Search ADCs implemented in n-type only technologies. Our methodology combines transistor-level defect characterization with system-level fault propagation analysis, enabling efficient exploration of both single and multiple fault scenarios across the conversion hierarchy. The framework identifies critical fault-sensitive circuit components and enables selective redundancy strategies targeting only the most sensitive components. The resulting defect-tolerant designs improve fault coverage from 60% to 92% under single-fault injections and from 34% to 77.6% under multi-fault injection, while incurring only 4.2% area overhead and 6% power increase. While validated on IGZO-TFTs, the methodology applies to all emerging unipolar technologies.