Scaling Routers with In-Package Optics and High-Bandwidth Memories

TL;DR

This paper introduces a novel high-bandwidth, scalable internet router architecture using in-package optics, chiplets, and HBM memories to achieve petabit/sec throughput within a single package, emphasizing power consumption considerations.

Contribution

It presents a new router design integrating in-package optics, chiplets, and HBM memories, with a split-parallel switch architecture and a novel traffic interleaving algorithm for scalable high-speed routing.

Findings

Achieves petabit/sec throughput in a single package.

Passive spatial division with minimal traffic imbalance.

HBM-based shared-memory architecture with cyclical interleaving.

Abstract

This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optics. We propose a novel internet router architecture that employs these technologies to achieve a petabit/sec router within a single integrated package. At the top-level, we introduce a novel split-parallel switch architecture that spatially divides (without processing) the incoming fibers and distributes them across smaller independent switches without intermediate OEO conversions or fine-tuned per-packet load-balancing. This passive spatial division enables scaling at the cost of a coarser traffic load balancing. Yet, through extensive evaluations of backbone network traffic, we demonstrate that differences with fine-tuned approaches are small. In addition, we propose a novel HBM-based shared-memory architecture for the implementation of the smaller independent switches, and we introduce a novel parallel frame interleaving algorithm that packs traffic into frames so that HBM banks are accessed at peak HBM data rates in a cyclical interleaving manner. We further discuss why these new technologies represent a paradigm shift in the design of future internet routers. Finally, we emphasize that power consumption may constitute the primary bottleneck to scaling.