ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs

TL;DR

ACE-RTL introduces a unified framework combining specialized RTL LLMs with frontier reasoning LLMs, significantly improving RTL code generation accuracy through iterative refinement and parallel debugging strategies.

Contribution

This work presents ACE-RTL, integrating domain-specific RTL models with agentic reasoning components for the first time in hardware design automation.

Findings

Achieves up to 41.02% pass rate improvement on CVDP benchmark.

Effectively combines specialized RTL models with frontier reasoning for better code correctness.

Reduces wall-clock iterations by parallelizing debugging trajectories.

Abstract

Recent advances in LLMs have sparked growing interest in applying them to hardware design automation, particularly for accurate RTL code generation. Prior efforts follow two largely independent paths: (i) training domain-adapted RTL models to internalize hardware semantics, (ii) developing agentic systems that leverage frontier generic LLMs guided by simulation feedback. However, these two paths exhibit complementary strengths and weaknesses. In this work, we present ACE-RTL that unifies both directions through Agentic Context Evolution (ACE). ACE-RTL integrates an RTL-specialized LLM, trained on a large-scale dataset of 1.7 million RTL samples, with a frontier reasoning LLM through three synergistic components: the generator, reflector, and coordinator. These components iteratively refine RTL code toward functional correctness. We further analyze a parallel scaling strategy that reduces wall-clock iterations to first success by exploring diverse debugging trajectories concurrently. On the CVDP benchmark, ACE-RTL achieves up to a 41.02% pass rate improvement over 14 competitive baselines.