Analysis of Edge Mismatch and Output Power Degradation in Cascoded Class-D Power Amplifiers Using Dual-Range Voltage Level Shifters

TL;DR

This paper introduces a high-speed, low-jitter hybrid voltage level shifter capable of operating up to 12.4 GHz, with a compact design and low power consumption, suitable for advanced high-speed applications.

Contribution

A novel hybrid voltage level shifter with cross-coupled feedback achieving high-speed operation and low jitter in 22-nm FD-SOI technology.

Findings

Operates up to 12.4 GHz

Consumes 4.43 μW per cycle

Jitter less than 150 fs-rms

Abstract

This paper presents a low-jitter hybrid voltage level shifter (HVLS) suitable for high-speed applications. The proposed architecture offers the advantage of cross-coupled feedback to simultaneously generate two voltage domain signals with available swings equal to the nominal supply and its double, which operate up to 12.4 GHz. A prototype HVLS circuit, along with impedance matching and a driver to enable high-speed off-chip testing, was fabricated in a 22-nm FD-SOI process technology. The prototype consumes a total die area, including the interface circuitry, of 477 x 462 um^2, while the active area of the level-shifter is 2 x 3.26 um^2. The average power consumption of the circuit is measured to be 4.43 uW per cycle, and the jitter is less than 150 fs-rms.