2.5D co-packaged optical I/O chipsets on a SiON/Si interposer for 4 $\times$ 100G optical interconnection
Daibao Hou, Yuntian Yao, Xiaotian Cheng, Shuning Ding, Qiyou Wu, Yonghong Hu, Wei Pan, Chao Huang, Huihui Zhu, Yongzhen Huang, Chenhui Li, and Chaoyuan Jin

TL;DR
This paper presents a SiON/Si-based optical interposer with integrated high-bandwidth optical I/O chipsets, demonstrating a 400-Gb/s transceiver with reliable high-speed data transmission suitable for high-performance computing clusters.
Contribution
The work introduces a novel SiON/Si optical interposer architecture integrating scalable waveguide routing and WDM with flip-chip active device integration, enabling high-speed, energy-efficient optical I/O.
Findings
Achieved 400-Gb/s data transmission with clear eye diagrams.
Demonstrated low-loss, thermally efficient optical interposer architecture.
Validated reliable high-speed data transfer in experimental setup.
Abstract
Optical I/O technologies have emerged as a potential industrial solution for high-performance data interconnection in AI/ML computing acceleration. While optical I/Os are deployed at the edge of computational chips by co-packaged optics (CPO), flexible and high-performance integration architectures need to be explored to address system-level challenges. In this work, we present and experimentally demonstrate a SiON/Si-based optical interposer that integrates high-bandwidth and energy-efficient optical I/O chipsets. High-performance photonic and electronic components are co-packaged on the interposer, leading to low-loss, signal-integrity-friendly, and thermally efficient characteristics. The optical interposer incorporates low-loss SiON photonic circuits to realize scalable waveguide routing and wavelength-division multiplexing (WDM) with polarization-insensitive operation and high…
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Taxonomy
TopicsSemiconductor Lasers and Optical Devices · Photonic and Optical Devices · 3D IC and TSV technologies
