Time Series Reasoning via Process-Verifiable Thinking Data Synthesis and Scheduling for Tailored LLM Reasoning
Jiahui Zhou, Dan Li, Boxin Li, Xiao Zhang, Erli Meng, Lin Li, Zhuomin Chen, Jian Lou, See-Kiong Ng

TL;DR
VeriTime is a framework that enhances LLMs for time series reasoning by synthesizing data, scheduling training samples effectively, and applying RL finetuning, leading to significant performance improvements.
Contribution
It introduces a novel data synthesis pipeline, a hierarchical data scheduling mechanism, and a two-stage RL finetuning process specifically for time series reasoning in LLMs.
Findings
Small models achieve reasoning performance comparable to larger models.
The framework significantly improves LLM performance on diverse time series tasks.
VeriTime's data synthesis and scheduling strategies are effective for training time series reasoning models.
Abstract
Time series is a pervasive data type across various application domains, rendering the reasonable solving of diverse time series tasks a long-standing goal. Recent advances in large language models (LLMs), especially their reasoning abilities unlocked through reinforcement learning (RL), have opened new opportunities for tackling tasks with long Chain-of-Thought (CoT) reasoning. However, leveraging LLM reasoning for time series remains in its infancy, hindered by the absence of carefully curated time series CoT data for training, limited data efficiency caused by underexplored data scheduling, and the lack of RL algorithms tailored for exploiting such time series CoT data. In this paper, we introduce VeriTime, a framework that tailors LLMs for time series reasoning through data synthesis, data scheduling, and RL training. First, we propose a data synthesis pipeline that constructs a…
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