LAAFD: LLM-based Agents for Accelerated FPGA Design

TL;DR

LAAFD leverages large language models to automate the translation of C++ code into optimized FPGA kernels, significantly reducing expert effort while maintaining high performance in HPC and stencil workloads.

Contribution

This paper introduces LAAFD, a novel LLM-based workflow that automates FPGA kernel optimization and verification, bridging the gap between high-level programming and efficient FPGA design.

Findings

Achieves 99.9% performance of hand-tuned Vitis HLS kernels.

Matches state-of-the-art stencil code generator performance.

Automates key FPGA optimizations with iterative feedback loop.

Abstract

FPGAs offer high performance, low latency, and energy efficiency for accelerated computing, yet adoption in scientific and edge settings is limited by the specialized hardware expertise required. High-level synthesis (HLS) boosts productivity over HDLs, but competitive designs still demand hardware-aware optimizations and careful dataflow design. We introduce LAAFD, an agentic workflow that uses large language models to translate general-purpose C++ into optimized Vitis HLS kernels. LAAFD automates key transfor mations: deep pipelining, vectorization, and dataflow partitioning and closes the loop with HLS co-simulation and synthesis feedback to verify correctness while iteratively improving execution time in cycles. Over a suite of 15 kernels representing common compute patterns in HPC, LAFFD achieves 99.9% geomean performance when compared to the hand tuned baseline for Vitis HLS. For stencil workloads, LAAFD matches the performance of SODA, a state-of-the-art DSL-based HLS code generator for stencil solvers, while yielding more readable kernels. These results suggest LAAFD substantially lowers the expertise barrier to FPGA acceleration without sacrificing efficiency.