Reducing the Computational Cost Scaling of Tensor Network Algorithms via Field-Programmable Gate Array Parallelism
Songtai Lv, Yang Liang, Rui Zhu, Qibin Zheng, Haiyuan Zou

TL;DR
This paper introduces a FPGA-based parallel tensor network algorithm design that significantly reduces computational costs and enhances scalability for quantum many-body calculations.
Contribution
It presents a novel FPGA-based parallelization strategy for tensor network algorithms, reducing computational complexity and enabling scalable hardware implementation.
Findings
Reduced computational cost scaling from O(D_b^3) to O(D_b) for iTEBD.
Reduced computational cost scaling from O(D_b^6) to O(D_b^2) for HOTRG.
Demonstrated superior scalability compared to CPU implementations.
Abstract
Improving the computational efficiency of quantum many-body calculations from a hardware perspective remains a critical challenge. Although field-programmable gate arrays (FPGAs) have recently been exploited to improve the computational scaling of algorithms such as Monte Carlo methods, their application to tensor network algorithms is still at an early stage. In this work, we propose a fine-grained parallel tensor network design based on FPGAs to substantially enhance the computational efficiency of two representative tensor network algorithms: the infinite time-evolving block decimation (iTEBD) and the higher-order tensor renormalization group (HOTRG). By employing a quad-tile partitioning strategy to decompose tensor elements and map them onto hardware circuits, our approach effectively translates algorithmic computational complexity into scalable hardware resource utilization,…
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Taxonomy
TopicsQuantum many-body systems · Quantum Computing Algorithms and Architecture · Machine Learning in Materials Science
