Quantum Sequential Circuits

TL;DR

This paper introduces quantum sequential circuits (QSCs), a new hardware-oriented quantum computing paradigm utilizing quantum transistors and topological junctions to enable memory and sequencing, advancing towards a quantum von Neumann architecture.

Contribution

It proposes a novel quantum circuit model based on quantum transistors and topological junctions, incorporating memory and feedback mechanisms for scalable quantum computing.

Findings

Defines quantum sequential circuits as a universal quantum computation model.

Demonstrates the use of symmetry-protected topological junctions and Choi states.

Lays groundwork for large-scale, integrated quantum information processors.

Abstract

This work introduces and characterizes quantum sequential circuits (QSCs) as a hardware-oriented paradigm for quantum computing, built upon a novel foundational element termed the quantum transistor. Unlike conventional qubit-based architectures, QSCs employ symmetry-protected topological junctions where quantum gates are encoded as Choi states via channel-state duality and activated through bulk measurements, utilizing ebits to realize the functional analog of feedback loops in classical sequential circuits. This framework establishes a universal model for quantum computation that inherently incorporates memory and temporal sequencing, complementing existing combinational quantum circuit model. Our work advances the conceptual bridge towards a quantum von Neumann architecture, underscoring the potential of hybrid and modular design principles for the development of large-scale, integrated quantum information processors.