Evolutionary Mapping of Neural Networks to Spatial Accelerators

TL;DR

This paper presents an evolutionary, hardware-in-the-loop framework that automates the mapping of neural network workloads onto spatial accelerators, significantly improving latency and energy efficiency.

Contribution

It introduces the first evolutionary mapping framework for neuromorphic accelerators, reducing reliance on expert knowledge and optimizing performance.

Findings

Up to 35% latency reduction on Intel Loihi 2

Up to 40% energy efficiency improvement

Scalable to multi-chip systems

Abstract

Spatial accelerators, composed of arrays of compute-memory integrated units, offer an attractive platform for deploying inference workloads with low latency and low energy consumption. However, fully exploiting their architectural advantages typically requires careful, expert-driven mapping of computational graphs to distributed processing elements. In this work, we automate this process by framing the mapping challenge as a black-box optimization problem. We introduce the first evolutionary, hardware-in-the-loop mapping framework for neuromorphic accelerators, enabling users without deep hardware knowledge to deploy workloads more efficiently. We evaluate our approach on Intel Loihi 2, a representative spatial accelerator featuring 152 cores per chip in a 2D mesh. Our method achieves up to 35% reduction in total latency compared to default heuristics on two sparse multi-layer perceptron networks. Furthermore, we demonstrate the scalability of our approach to multi-chip systems and observe an up to 40% improvement in energy efficiency, without explicitly optimizing for it.