Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security

TL;DR

Crypto-RV is a high-efficiency FPGA-based RISC-V co-processor that unifies support for multiple cryptographic algorithms, significantly improving speed and energy efficiency for IoT security applications.

Contribution

The paper introduces Crypto-RV, a novel RISC-V cryptographic co-processor architecture with architectural innovations for unified, high-performance cryptographic processing on FPGA.

Findings

Achieves up to 1,061x speedup over baseline cores.

Offers 5.8x to 17.4x better energy efficiency than powerful CPUs.

Occupies minimal FPGA resources, suitable for IoT devices.

Abstract

Cryptographic operations are critical for securing IoT, edge computing, and autonomous systems. However, current RISC-V platforms lack efficient hardware support for comprehensive cryptographic algorithm families and post-quantum cryptography. This paper presents Crypto-RV, a RISC-V co-processor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Crypto-RV introduces three key architectural innovations: a high-bandwidth internal buffer (128x64-bit), cryptography-specialized execution units with four-stage pipelined datapaths, and a double-buffering mechanism with adaptive scheduling optimized for large-hash. Implemented on Xilinx ZCU102 FPGA at 160 MHz with 0.851 W dynamic power, Crypto-RV achieves 165 times to 1,061 times speedup over baseline RISC-V cores, 5.8 times to 17.4 times better energy efficiency compared to powerful CPUs. The design occupies only 34,704 LUTs, 37,329 FFs, and 22 BRAMs demonstrating viability for high-performance, energy-efficient cryptographic processing in resource-constrained IoT environments.