Position: The Need for Ultrafast Training

TL;DR

This paper advocates for developing ultrafast on-chip training for FPGAs to enable real-time learning and adaptation in high-frequency, non-stationary environments, expanding FPGA applications beyond static inference.

Contribution

It introduces the concept of integrating training directly into FPGA fabric, proposing a paradigm shift from inference-only accelerators to real-time learning systems.

Findings

Highlights the limitations of current static inference accelerators.

Proposes a new architecture for ultrafast on-chip training.

Discusses potential applications in scientific and industrial domains.

Abstract

Domain-specialized FPGAs have delivered unprecedented performance for low-latency inference across scientific and industrial workloads, yet nearly all existing accelerators assume static models trained offline, relegating learning and adaptation to slower CPUs or GPUs. This separation fundamentally limits systems that must operate in non-stationary, high-frequency environments, where model updates must occur at the timescale of the underlying physics. In this paper, I argue for a shift from inference-only accelerators to ultrafast on-chip learning, in which both inference and training execute directly within the FPGA fabric under deterministic, sub-microsecond latency constraints. Bringing learning into the same real-time datapath as inference would enable closed-loop systems that adapt as fast as the physical processes they control, with applications spanning quantum error correction, cryogenic qubit calibration, plasma and fusion control, accelerator tuning, and autonomous scientific experiments. Enabling such regimes requires rethinking algorithms, architectures, and toolflows jointly, but promises to transform FPGAs from static inference engines into real-time learning machines.