LocalV: Exploiting Information Locality for IP-level Verilog Generation

TL;DR

LocalV introduces a multi-agent framework that exploits information locality to improve IP-level Verilog code generation, addressing scalability and correctness issues faced by existing LLM-based approaches.

Contribution

It presents a novel hierarchical, locality-aware approach combining document partitioning, task planning, and debugging to enhance large-scale hardware description generation.

Findings

LocalV achieves a 45.0% pass rate on RealBench, outperforming SOTA LLMs.

Decomposing tasks into localized subproblems improves code correctness.

The framework effectively handles long, detailed hardware design documents.

Abstract

The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design, traditionally requiring engineers to manually translate complex specifications into thousands of lines of synthesizable Hardware Description Language (HDL) code. While Large Language Models (LLMs) have shown promise in automating this process, existing approaches-including fine-tuned domain-specific models and advanced agent-based systems-struggle to scale to industrial IP-level design tasks. We identify three key challenges: (1) handling long, highly detailed documents, where critical interface constraints become buried in unrelated submodule descriptions; (2) generating long RTL code, where both syntactic and semantic correctness degrade sharply with increasing output length; and (3) navigating the complex debugging cycles required for functional verification through simulation and waveform analysis. To overcome these challenges, we propose LocalV, a multi-agent framework that leverages information locality in modular hardware design. LocalV decomposes the long-document to long-code generation problem into a set of short-document, short-code tasks, enabling scalable generation and debugging. Specifically, LocalV integrates hierarchical document partitioning, task planning, localized code generation, interface-consistent merging, and AST-guided locality-aware debugging. Experiments on RealBench, an IP-level Verilog generation benchmark, demonstrate that LocalV substantially outperforms state-of-the-art (SOTA) LLMs and agents, achieving a pass rate of 45.0% compared to 21.6%.