Weight-four parity checks with silicon spin qubits

TL;DR

This paper demonstrates a silicon spin-qubit device capable of performing weight-four parity checks essential for quantum error correction, using shuttling and QND measurements to control a five-qubit array and generate large entangled states.

Contribution

It introduces a scalable silicon spin-qubit architecture with dynamic connectivity and demonstrates weight-four parity checks and multi-qubit entanglement in a five-qubit system.

Findings

Achieved universal control of a five-qubit processor.

Demonstrated weight-four parity checks for quantum error correction.

Generated a five-qubit GHZ state with genuine entanglement.

Abstract

Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we demonstrate a silicon spin-qubit device that comprises a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight-four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays.