In-situ benchmarking of fault-tolerant quantum circuits. I. Clifford circuits

TL;DR

This paper introduces an in-situ benchmarking method for fault-tolerant quantum circuits that uses syndrome data to characterize physical and logical errors efficiently, providing an exponential advantage over existing methods.

Contribution

It develops a scheme to estimate Pauli noise and predict logical fidelities directly from syndrome data in Clifford circuits, with polynomial sample complexity.

Findings

Accurately predicts logical fidelities from syndrome data

Requires only polynomial sample size for noise estimation

Demonstrated on synthetic and experimental data

Abstract

Benchmarking physical devices and verifying logical algorithms are important tasks for scalable fault-tolerant quantum computing. Numerous protocols exist for benchmarking devices before running actual algorithms. In this work, we show that both physical and logical errors of fault-tolerant circuits can even be characterized in-situ using syndrome data. To achieve this, we map general fault-tolerant Clifford circuits to subsystem codes using the spacetime code formalism and develop a scheme for estimating Pauli noise in Clifford circuits using syndrome data. We give necessary and sufficient conditions for the learnability of physical and logical noise from given syndrome data, and show that we can accurately predict logical fidelities from the same data. Importantly, our approach requires only a polynomial sample size, even when the logical error rate is exponentially suppressed by the code distance, and thus gives an exponential advantage against methods that use only logical data such as direct fidelity estimation. We demonstrate the practical applicability of our methods in various scenarios using synthetic data as well as the experimental data from a recent demonstration of fault-tolerant circuits by Bluvstein et al. [Nature 626, 7997 (2024)]. Our methods provide an efficient, in-situ way of characterizing a fault-tolerant quantum computer to help gate calibration, improve decoding accuracy, and verify logical circuits.