The First Switch Effect in Ferroelectric Field-Effect Transistors

TL;DR

This paper identifies the 'First Switch Effect' in ferroelectric FETs, where the initial write pulse causes most trap generation, significantly impacting device endurance and interface trap density.

Contribution

It reveals the dominant role of the first write pulse in trap formation and establishes a direct link between polarization switching and interface trap density in FEFETs.

Findings

The first write pulse generates over 50% of total traps.

Trap density near the interface is highest after the first switch.

Further cycling generates traps deeper in the device stack.

Abstract

In this work, a ferroelectric field-effect transistor (FEFET) is systematically characterized and compared with an equivalent standard MOSFET with an equivalent oxide thickness. We show that these two devices, with a silicon channel, exhibit similar pristine state transfer characteristics but starkly different endurance characteristics. In contrast to the MOSFET, the FEFET shows a significant increase in sub-threshold swing in the first write pulse. Based on this, we reveal that this first write pulse (cycle 1) generates more than half of the total traps generated during the fatigue cycling in FEFETs. We call this the 'First Switch Effect'. Further, by polarizing a pristine FEFET step by step, we demonstrate a direct correlation between the switched polarization and interface trap density during the first switch. Through charge pumping measurements, we also observe that continued cycling generates traps more towards the bulk of the stack, away from the Si/SiO2 interface in FEFETs. We establish that: (1) the first switch effect leads to approximately 50% of the total trap density (Nit) near the Si/SiO2 interface until memory window closure; and (2) further bipolar cycling leads to trap generation both at and away from Si/SiO2 interface in FEFETs.