Echo Cross Resonance gate error budgeting on a superconducting quantum processor

TL;DR

This paper presents an error budgeting and suppression method for superconducting quantum processors that significantly reduces two-qubit gate errors, improving overall device performance and uniformity.

Contribution

It introduces an error budgeting procedure and suppression techniques that require no extra hardware, leading to a 3.7x average error reduction on a 32-qubit system.

Findings

Average 3.7x reduction in two-qubit gate errors

Median error rate improved from 4.6% to 1.2%

Enhanced performance on previously under-performing qubit pairs

Abstract

High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6$\%$ to 1.2$\%$ as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.