On Efficient Polyphase Network Implementation Using Successive Vector Approximation

TL;DR

This paper presents a novel, energy-efficient method for implementing polyphase networks in FBMC systems by converting to a sum of signed powers of two, enabling multiplierless hardware with improved performance.

Contribution

Introduces a greedy matching pursuit algorithm for direct conversion to SOPOT representation, enhancing multiplierless polyphase network implementation.

Findings

Achieves superior performance compared to existing methods

Maintains similar computational complexity

Enables efficient, multiplierless hardware design

Abstract

In this work, we explore an energy-efficient implementation of the polyphase network for a filter bank multicarrier (FBMC) system. The network is approximated using a greedy algorithm based on matching pursuits (MP) that converts the numerical representation directly from floating point to sum of signed powers of two (SOPOT), which is key for a multiplierless implementation. We compare this technique with other state-of-the-art methods for designing multiplierless hardware, and show that our technique achieves superior performance with similar computational complexity.