Continuous-Flow Data-Rate-Aware CNN Inference on FPGA

TL;DR

This paper introduces a novel data-rate-aware FPGA architecture for CNN inference that maintains high hardware utilization and throughput by intelligently managing data flow and sharing resources.

Contribution

It presents a new approach to designing continuous-flow CNN architectures on FPGA that adapt to data rate reductions, improving efficiency and enabling complex CNNs like MobileNet.

Findings

High hardware utilization close to 100% achieved

Significant logic savings enable complex CNNs on FPGA

High throughput maintained for various CNN architectures

Abstract

Among hardware accelerators for deep-learning inference, data flow implementations offer low latency and high throughput capabilities. In these architectures, each neuron is mapped to a dedicated hardware unit, making them well-suited for field-programmable gate array (FPGA) implementation. Previous unrolled implementations mostly focus on fully connected networks because of their simplicity, although it is well known that convolutional neural networks (CNNs) require fewer computations for the same accuracy. When observing the data flow in CNNs, pooling layers and convolutional layers with a stride larger than one, the number of data at their output is reduced with respect to their input. This data reduction strongly affects the data rate in a fully parallel implementation, making hardware units heavily underutilized unless it is handled properly. This work addresses this issue by analyzing the data flow of CNNs and presents a novel approach to designing data-rate-aware, continuous-flow CNN architectures. The proposed approach ensures a high hardware utilization close to 100% by interleaving low data rate signals and sharing hardware units, as well as using the right parallelization to achieve the throughput of a fully parallel implementation. The results show that a significant amount of the arithmetic logic can be saved, which allows implementing complex CNNs like MobileNet on a single FPGA with high throughput.