GTAC: A Generative Transformer for Approximate Circuits

TL;DR

GTAC introduces a novel generative Transformer-based framework for approximate circuit synthesis, significantly improving power, delay, and area metrics by leveraging a partitioned, error-bounded generation approach.

Contribution

It pioneers the use of Transformer models with a novel irredundant encoding for scalable, error-aware approximate circuit generation, surpassing traditional ALS methods.

Findings

Reduces delay by 30.9% and gate count by 50.5% over exact baselines.

Achieves 6.5% area savings with a 4.3x speedup compared to traditional ALS.

Reduces sequence length by 33.3x and peak memory by 61.6x with irredundant encoding.

Abstract

Targeting error-tolerant applications, approximate computing relaxes rigid functional equivalence to significantly improve power, performance, and area. Traditional approximate logic synthesis (ALS) relies on incremental rewriting, limiting design space exploration. Meanwhile, the inherently probabilistic nature of Transformer-based generative AI makes it a natural fit for generating approximate circuits. Exploiting this, we propose GTAC, an end-to-end framework for arbitrary-scale generative ALS. To overcome the memory bottleneck of generative AI, GTAC partitions a large circuit into tractable subcircuits, applies a generative core to produce approximate candidates for each subcircuit, and finally selects proper candidates to form the final design. Its core generative Transformer utilizes a novel irredundant encoding to compactly encode a circuit, alongside a masking mechanism to exclude designs violating the given error bound. Empowered by a self-evolutionary training strategy, GTAC establishes a new paradigm that demonstrates superior performance: It reduces delay by 30.9% and gate count by 50.5% over exact generative baselines and saves 6.5% area with a 4.3x speedup against traditional ALS methods. Furthermore, its irredundant encoding achieves a 33.3x reduction in sequence length and a 61.6x reduction in peak memory compared to conventional memoryless traversal.