A Folded Surface Code Architecture for 2D Quantum Hardware

TL;DR

This paper introduces a 2D quantum hardware architecture utilizing folded surface codes and shuttling, enabling faster logical gate operations and more efficient magic-state distillation, advancing scalable quantum computing.

Contribution

It demonstrates how folded surface codes can be implemented on 2D hardware with shuttling, significantly reducing logical gate runtimes and magic-state distillation volume.

Findings

Constant-time logical Clifford gates and CNOTs in 2D surface codes.

Order-of-magnitude reduction in magic-state distillation volume.

Introduction of a virtual-stack layout for efficient multilayer routing.

Abstract

Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from $\mathcal{O}(d)$ in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal $S$ gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.