Inter-branch message transfer on superconducting quantum processors: a multi-architecture benchmark

TL;DR

This paper benchmarks inter-branch message transfer on superconducting quantum processors, analyzing performance across different architectures and message types to understand noise effects and routing overhead without error mitigation.

Contribution

It introduces a practical benchmark for near-term quantum processors using inter-branch message transfer, comparing multiple architectures and message families without error mitigation.

Findings

Sparse messages achieve constant two-qubit depth, revealing device noise levels.

Routing overhead increases rapidly for half and dense messages, affecting performance.

Variability due to transpiler seeds is significant near the coherence limit.

Abstract

We treat inter-branch message transfer in a Wigner's-friend circuit as a practical benchmark for near-term superconducting quantum processors. Implementing Violaris' unitary message-transfer primitive, we compare performance across IBM Eagle, Nighthawk, and Heron (r2/r3) processors for message sizes up to $n=32$, without error mitigation. We study three message families -- sparse (one-hot), half-weight, and dense -- and measure conditional string success $p_{\mathrm{all}}=\Pr(P=\mu\mid R=0)$, memory erasure after uncomputation, and correlation diagnostics (branch contrast and bitwise mutual information). The sparse family compiles to essentially constant two-qubit depth, yielding a depth-controlled probe of device noise: at $n=32$ we observe $p_{\mathrm{all}}$ spanning $\approx0.07$ to $\approx0.68$ across backends. In contrast, half and dense messages incur rapidly growing routing overhead, and transpiler-seed variability becomes a practical limitation near the coherence frontier. We further report an amplitude sweep (no-amplification test) and a divergence ``cousins'' sweep that quantifies degradation with branch-conditioned complexity. All data and figure-generation scripts are released.