RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version)

TL;DR

RTeAAL Sim introduces a tensor algebra-based approach to RTL simulation, significantly reducing compilation overhead and CPU bottlenecks, and achieving performance comparable to established simulators.

Contribution

It reformulates RTL simulation as a sparse tensor algebra problem, enabling new optimizations and decoupling simulation from binary size.

Findings

Mitigates compilation overhead and instruction-cache pressure.

Achieves performance competitive with Verilator.

Demonstrates effectiveness across multiple CPUs and ISAs.

Abstract

RTL simulation on CPUs remains a persistent bottleneck in hardware design. State-of-the-art simulators embed the circuit directly into the simulation binary, resulting in long compilation times and execution that is fundamentally CPU frontend-bound, with severe instruction-cache pressure. This work proposes RTeAAL Sim, which reformulates RTL simulation as a sparse tensor algebra problem. By representing RTL circuits as tensors and simulation as a sparse tensor algebra kernel, RTeAAL Sim decouples simulation behavior from binary size and makes RTL simulation amenable to well-studied tensor algebra optimizations. We demonstrate that a prototype of our tensor-based simulator, even with a subset of these optimizations, already mitigates the compilation overhead and frontend pressure and achieves performance competitive with the highly optimized Verilator simulator across multiple CPUs and ISAs.