EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization

TL;DR

EvolVE introduces a novel evolutionary framework utilizing different strategies and benchmarks to automate and optimize Verilog hardware design with state-of-the-art results, addressing the limitations of LLMs in hardware logic reasoning.

Contribution

This work is the first to analyze multiple evolution strategies for chip design, introduce industry-scale benchmarks, and achieve state-of-the-art results in Verilog generation and optimization.

Findings

MCTS maximizes functional correctness

IGR excels in optimization tasks

Achieved 98.1% accuracy on VerilogEval v2

Abstract

Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation, their limited training data and intrinsic sequential reasoning fail to capture the strict formal logic and concurrency inherent in hardware systems. To overcome these barriers, we present EvolVE, the first framework to analyze multiple evolution strategies on chip design tasks, revealing that Monte Carlo Tree Search (MCTS) excels at maximizing functional correctness, while Idea-Guided Refinement (IGR) proves superior for optimization. We further leverage Structured Testbench Generation (STG) to accelerate the evolutionary process. To address the lack of complex optimization benchmarks, we introduce IC-RTL, targeting industry-scale problems derived from the National Integrated Circuit Contest. Evaluations establish EvolVE as the new state-of-the-art, achieving 98.1% on VerilogEval v2 and 92% on RTLLM v2. Furthermore, on the industry-scale IC-RTL suite, our framework surpasses reference implementations authored by contest participants, reducing the Power, Performance, Area (PPA) product by up to 66% in Huffman Coding and 17% in the geometric mean across all problems. The source code of the IC-RTL benchmark is available at https://github.com/weiber2002/ICRTL.