Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

TL;DR

This paper introduces a memory-efficient FPGA implementation of a stochastic simulated annealing algorithm that converges faster and uses less memory than traditional methods, significantly improving performance on combinatorial optimization problems.

Contribution

The paper presents a hardware-aware SSA algorithm optimized for FPGA that reduces memory usage and accelerates convergence compared to conventional SSA and SA methods.

Findings

Up to 114-times faster convergence than conventional SA.

Up to 6-times memory efficiency improvement on FPGA.

Maintains high solution quality for maximum cut problems.

Abstract

Simulated annealing (SA) is a well-known algorithm for solving combinatorial optimization problems. However, the computation time of SA increases rapidly, as the size of the problem grows. Recently, a stochastic simulated annealing (SSA) algorithm that converges faster than conventional SA has been reported. In this paper, we present a hardware-aware SSA (HA- SSA) algorithm for memory-efficient FPGA implementations. HA-SSA can reduce the memory usage of storing intermediate results while maintaining the computing speed of SSA. For evaluation purposes, the proposed algorithm is compared with the conventional SSA and SA approaches on maximum cut combinatorial optimization problems. HA-SSA achieves a convergence speed that is up to 114-times faster than that of the conventional SA algorithm depending on the maximum cut problem selected from the G-set which is a dataset of the maximum cut problems. HA-SSA is implemented on a field-programmable gate array (FPGA) (Xilinx Kintex-7), and it achieves up to 6-times the memory efficiency of conventional SSA while maintaining high solution quality for optimization problems.