Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V Cores

TL;DR

This paper presents COPIFTv2, an improved method for dual-issue execution on lightweight RISC-V cores, achieving higher speed and energy efficiency by simplifying communication and synchronization between instruction threads.

Contribution

COPIFTv2 introduces lightweight queues for direct communication, reducing complexity and overhead compared to prior dual-issue execution methods on RISC-V cores.

Findings

Up to 1.49x speedup over COPIFT

Up to 1.47x energy efficiency gain

Peak IPC of 1.81 achieved

Abstract

Large-scale ML accelerators rely on large numbers of PEs, imposing strict bounds on the area and energy budget of each PE. Prior work demonstrates that limited dual-issue capabilities can be efficiently integrated into a lightweight in-order open-source RISC-V core (Snitch), with a geomean IPC boost of 1.6x and a geomean energy efficiency gain of 1.3x, obtained by concurrently executing integer and FP instructions. Unfortunately, this required a complex and error-prone low level programming model (COPIFT). We introduce COPIFTv2 which augments Snitch with lightweight queues enabling direct, fine-grained communication and synchronization between integer and FP threads. By eliminating the tiling and software pipelining steps of COPIFT, we can remove much of its complexity and software overheads. As a result, COPIFTv2 achieves up to a 1.49x speedup and a 1.47x energy-efficiency gain over COPIFT, and a peak IPC of 1.81. Overall, COPIFTv2 significantly enhances the efficiency and programmability of dual-issue execution on lightweight cores. Our implementation is fully open source and performance experiments are reproducible using free software.