@NTT: Algorithm-Targeted NTT hardware acceleration via Design-Time Constant Optimization

TL;DR

This paper introduces @NTT, a hardware acceleration technique for the Number Theoretic Transform that leverages fixed ring parameters for design-time optimization, achieving high throughput and compact footprint in cryptographic applications.

Contribution

The paper presents a novel design-time constant optimization method for NTT hardware, enabling maximum throughput with reduced hardware resources in lattice-based cryptography.

Findings

Achieves 1.0 GHz clock frequency on TSMC 28 nm process.

Operates with a hardware footprint of 1.45 mm^2.

FPGA implementation outperforms state-of-the-art by 5.2x in throughput-per-LUT.

Abstract

The Number Theoretic Transform (NTT) is a critical computational bottleneck in many lattice-based postquantum cryptographic (PQC) algorithms. By leveraging the Fast Fourier Transform (FFT) algorithm, the NTT of a polynomial of degree N - 1 can be computed with a time complexity of O(N log N). Hardware implementation of NTT is generally preferred over software ones, as the latter are significantly slower due to complex memory access patterns and modular arithmetic operations. Achieving maximum throughput in hardware, however, typically demands a prohibitively large number of butterfly unit instantiations. In this work, we propose @NTT, which exploits the fact that the ring parameters in these algorithms are fixed, enabling design-time constant optimization and achieving the maximum throughput of N-point NTT per clock cycle with a compact hardware footprint. Our case study on the Dilithium NTT, implemented using the TSMC 28 nm library, operates at a clock frequency of 1.0 GHz with an area of 1.45 mm^2. On FPGA, the design achieves a throughput-per-LUT that is 5.2x higher than the state-of-the-art implementation.