SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency

TL;DR

SPADE is a novel SIMD Posit-based compute engine that efficiently supports multiple precisions for DNN acceleration, offering significant hardware savings and robust numerical performance for edge-AI applications.

Contribution

It introduces a unified multi-precision SIMD Posit architecture with a regime-aware, lane-fused datapath that reuses modules across precisions without duplication.

Findings

FPGA implementation reduces LUT and slice usage significantly.

ASIC implementation achieves high frequency at low power.

Maintains competitive accuracy on standard datasets.

Abstract

The growing demand for edge-AI systems requires arithmetic units that balance numerical precision, energy efficiency, and compact hardware while supporting diverse formats. Posit arithmetic offers advantages over floating- and fixed-point representations through its tapered precision, wide dynamic range, and improved numerical robustness. This work presents SPADE, a unified multi-precision SIMD Posit-based multiplyaccumulate (MAC) architecture supporting Posit (8,0), Posit (16,1), and Posit (32,2) within a single framework. Unlike prior single-precision or floating/fixed-point SIMD MACs, SPADE introduces a regime-aware, lane-fused SIMD Posit datapath that hierarchically reuses Posit-specific submodules (LOD, complementor, shifter, and multiplier) across 8/16/32-bit precisions without datapath replication. FPGA implementation on a Xilinx Virtex-7 shows 45.13% LUT and 80% slice reduction for Posit (8,0), and up to 28.44% and 17.47% improvement for Posit (16,1) and Posit (32,2) over prior work, with only 6.9% LUT and 14.9% register overhead for multi-precision support. ASIC results across TSMC nodes achieve 1.38 GHz at 6.1 mW (28 nm). Evaluation on MNIST, CIFAR-10/100, and alphabet datasets confirms competitive inference accuracy.