Pipeline Automation Framework for Reusable High-throughput Network Applications on FPGA

TL;DR

This paper presents PAF, an open-source framework that automates FPGA pipeline design, enabling scalable, reusable, and optimized network applications across diverse FPGA targets with minimal code and maintained performance.

Contribution

Introduction of PAF, a pipeline automation framework based on Chisel, that simplifies FPGA network application deployment and enhances reusability and optimization across multiple FPGA platforms.

Findings

PAF enables efficient parameterization of FPGA pipelines.

PAF reduces code complexity for complex functionalities.

PAF achieves performance and resource usage comparable to manual designs.

Abstract

In a context of ever-growing worldwide communication traffic, cloud service providers aim at deploying scalable infrastructures to address heterogeneous needs. Part of the network infrastructure, FPGAs are tailored to guarantee low-latency and high-throughput packet processing. However, slowness of the hardware design process impairs FPGA ability to be part of an agile infrastructure under constant evolution, from incident response to long-term transformation. Deploying and maintaining network functionalities across a wide variety of FPGAs raises the need to fine-tune hardware designs for several FPGA targets. To address this issue, we introduce PAF, an open-source architectural parameterization framework based on a pipeline-oriented design methodology. PAF (Pipeline Automation Framework) implementation is based on Chisel, a Scala-embedded Hardware Construction Language (HCL), that we leverage to interface with circuit elaboration. Applied to industrial network packet classification systems, PAF demonstrates efficient parameterization abilities, enabling to reuse and optimize the same pipelined design on several FPGAs. In addition, PAF focuses the pipeline description on the architectural intent, incidentally reducing the number of lines of code to express complex functionalities. Finally, PAF confirms that automation does not imply any loss of tight control on the architecture by achieving on par performance and resource usage with equivalent exhaustively described implementations.