Analysis of Sensing in OFDM-based ISAC under the Influence of Sampling Jitter
Lucas Giroto, \^Andrei Camponogara, Yueheng Li, Jiayi Chen, Lukas Sigg, Thomas Zwick, Benjamin Nuss

TL;DR
This paper investigates how sampling jitter affects OFDM-based integrated sensing and communication systems, revealing that hardware can mitigate degradation if jitter remains below a certain threshold.
Contribution
It provides a detailed analysis of sampling jitter impacts on OFDM-based ISAC, including distortion mechanisms and performance thresholds for baseband and bandpass sampling.
Findings
SJ causes intercarrier interference in baseband sampling.
SJ induces phase errors and severe interference in bandpass sampling.
Hardware can achieve femtosecond-level jitter, ensuring system robustness.
Abstract
To enable integrated sensing and communication (ISAC) in cellular networks, a wide range of additional requirements and challenges are either imposed or become more critical. One such impairment is sampling jitter (SJ), which arises due to imperfections in the sampling instants of the clocks of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). While SJ is already well studied for communication systems based on orthogonal frequency-division multiplexing (OFDM), which is expected to be the waveform of choice for most sixth-generation (6G) scenarios where ISAC could be possible, the implications of SJ on the OFDM-based radar sensing must still be thoroughly analyzed. Considering that phase-locked loop (PLL)-based oscillators are used to derive sampling clocks, which leads to colored SJ, i.e., SJ with non-flat power spectral density, this article analyzes the…
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Taxonomy
TopicsPAPR reduction in OFDM · Radar Systems and Signal Processing · Advancements in PLL and VCO Technologies
