GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling

TL;DR

This paper presents a GPU-accelerated simulated annealing framework based on p-bits that models real-world device variability, achieving significant speedups and revealing that variability can sometimes enhance performance.

Contribution

It introduces an open-source, CUDA-based simulation framework for p-bit probabilistic computing that incorporates real device variability factors, enabling scalable and realistic modeling.

Findings

Device variability can improve algorithm performance.

Achieved two-order magnitude speedup over CPU implementations.

Framework effectively models real-world device behavior.

Abstract

Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and machine learning. Realizing p-bits with emerging devices such as magnetic tunnel junctions (MTJs) introduces device variability, which was expected to negatively impact computational performance. However, this study reveals an unexpected finding: device variability can not only degrade but also enhance algorithm performance, particularly by leveraging timing variability. This paper introduces a GPU-accelerated, open-source simulated annealing framework based on p-bits that models key device variability factors -- timing, intensity, and offset -- to reflect real-world device behavior. Through CUDA-based simulations, our approach achieves a two-order magnitude speedup over CPU implementations on the MAX-CUT benchmark with problem sizes ranging from 800 to 20,000 nodes. By providing a scalable and accessible tool, this framework aims to advance research in probabilistic computing, enabling optimization applications in diverse fields.