Bit-Efficient Quantisation for Two-Channel Modulo-Sampling Systems

TL;DR

This paper introduces a bit-efficient quantisation method for two-channel modulo ADCs that reduces bitrate overhead by exploiting inter-channel differences, enabling high-resolution, bandwidth-efficient signal sensing.

Contribution

It proposes a novel quantisation scheme that transmits one channel output with a compact difference index, significantly reducing bitrate compared to existing methods.

Findings

Requires only 1-2 bits per sample overhead

Maintains comparable reconstruction accuracy

Demonstrates substantial bitrate savings in hardware experiments

Abstract

Two-channel modulo analog-to-digital converters (ADCs) enable high-dynamic-range signal sensing at the Nyquist rate per channel, but existing designs quantise both channel outputs independently, incurring redundant bitrate costs. This paper proposes a bit-efficient quantisation scheme that exploits the integer-valued structure of inter-channel differences, transmitting one quantised channel output together with a compact difference index. We prove that this approach requires only 1-2 bits per signal sample overhead relative to conventional ADCs, despite operating with a much smaller per-channel dynamic range. Simulations confirm the theoretical error bounds and bitrate analysis, while hardware experiments demonstrate substantial bitrate savings compared with existing modulo sampling schemes, while maintaining comparable reconstruction accuracy. These results highlight a practical path towards high-resolution, bandwidth-efficient modulo ADCs for bitrate-constrained systems.