The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization

TL;DR

This paper introduces cross-layer analysis tools and design strategies to improve the reliability and efficiency of AI accelerators facing nanoscale aging and variation effects.

Contribution

It presents a systematic framework for reliability-aware AI accelerator design, integrating cross-layer modeling and workload-specific optimizations.

Findings

Developed aging and variation-aware timing analysis tools

Optimized dataflow for critical input pattern reduction

Designed resilient architectures for large language models

Abstract

As the CMOS technology pushes to the nanoscale, aging effects and process variations have become increasingly pronounced, posing significant reliability challenges for AI accelerators. Traditional guardband-based design approaches, which rely on pessimistic timing margin, sacrifice significant performance and computational efficiency, rendering them inadequate for high-performance AI computing demands. Current reliability-aware AI accelerator design faces two core challenges: (1) the lack of systematic cross-layer analysis tools to capture coupling reliability effects across device, circuit, architecture, and application layers; and (2) the fundamental trade-off between conventional reliability optimization and computational efficiency. To address these challenges, this paper systematically presents a series of reliability-aware accelerator designs, encompassing (1) aging and variation-aware dynamic timing analyzer, (2) accelerator dataflow optimization using critical input pattern reduction, and (3) resilience characterization and novel architecture design for large language models (LLMs). By tightly integrating cross-layer reliability modeling and AI workload characteristics, these co-optimization approaches effectively achieve reliable and efficient AI acceleration.