RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs

TL;DR

RidgeWalker is a novel FPGA-based accelerator for graph random walks that leverages the Markov property to enable perfect pipelining and out-of-order execution, significantly improving performance over existing solutions.

Contribution

It introduces a new asynchronous pipeline architecture with a feedback-driven scheduler for efficient, out-of-order execution of graph random walks on FPGAs.

Findings

Achieves 7.0x speedup over state-of-the-art FPGA solutions

Achieves 8.1x speedup over GPU solutions

Peak speedups of up to 71.0x and 22.9x

Abstract

Graph Random Walks (GRWs) offer efficient approximations of key graph properties and have been widely adopted in many applications. However, GRW workloads are notoriously difficult to accelerate due to their strong data dependencies, irregular memory access patterns, and imbalanced execution behavior. While recent work explores FPGA-based accelerators for GRWs, existing solutions fall far short of hardware potential due to inefficient pipelining and static scheduling. This paper presents RidgeWalker, a high-performance GRW accelerator designed for datacenter FPGAs. The key insight behind RidgeWalker is that the Markov property of GRWs allows decomposition into stateless, fine-grained tasks that can be executed out-of-order without compromising correctness. Building on this, RidgeWalker introduces an asynchronous pipeline architecture with a feedback-driven scheduler grounded in queuing theory, enabling perfect pipelining and adaptive load balancing. We prototype RidgeWalker on datacenter FPGAs and evaluated it across a range of GRW algorithms and real-world graph datasets. Experimental results demonstrate that RidgeWalker achieves an average speedup of 7.0x over state-of-the-art FPGA solutions and 8.1x over GPU solutions, with peak speedups of up to 71.0x and 22.9x, respectively. The source code is publicly available at https://github.com/Xtra-Computing/RidgeWalker.