A Compute and Communication Runtime Model for Loihi 2
Jonathan Timcheck, Alessandro Pierro, Sumit Bam Shrestha

TL;DR
This paper introduces a novel max-affine lower-bound runtime model for Intel's Loihi 2 neuromorphic chip, accurately predicting compute and communication times to aid in designing efficient algorithms.
Contribution
It presents the first multi-dimensional roofline model for Loihi 2 that accounts for both compute and communication, validated with microbenchmarks and real workloads.
Findings
Model shows high correlation (≥0.97) with actual runtime measurements.
Reveals an area-runtime tradeoff in neural network layers.
Enables analysis of scalability and bottlenecks in neuromorphic computing.
Abstract
Neuromorphic computers hold the potential to vastly improve the speed and efficiency of a wide range of computational kernels with their asynchronous, compute-memory co-located, spatially distributed, and scalable nature. However, performance models that are simple yet sufficiently expressive to predict runtime on actual neuromorphic hardware are lacking, posing a challenge for researchers and developers who strive to design fast algorithms and kernels. As breaking the memory bandwidth wall of conventional von-Neumann architectures is a primary neuromorphic advantage, modeling communication time is especially important. At the same time, modeling communication time is difficult, as complex congestion patterns arise in a heavily-loaded Network-on-Chip. In this work, we introduce the first max-affine lower-bound runtime model -- a multi-dimensional roofline model -- for Intel's Loihi 2…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices
