Probabilistic Computers for MIMO Detection: From Sparsification to 2D Parallel Tempering
M Mahmudul Hasan Sajeeb, Corentin Delacour, Kevin Callahan-Coray, Sanjay Seshan, Tathagata Srimani, Kerem Y. Camsari

TL;DR
This paper presents a scalable on-chip probabilistic computing approach using p-bits and graph sparsification to efficiently solve dense MIMO detection problems, achieving low error rates and fast solution times.
Contribution
It introduces a novel graph sparsification method with auxiliary variables and a 2D parallel tempering algorithm for on-chip MIMO detection, improving convergence and scalability.
Findings
Achieved 4.7 ms end-to-end solution time per instance.
Demonstrated low bit error rates below linear detectors.
Projected 90 MHz operation with <200 mW power in 7 nm ASIC.
Abstract
Probabilistic computers built from p-bits offer a promising path for combinatorial optimization, but the dense connectivity required by real-world problems scales poorly in hardware. Here, we address this through graph sparsification with auxiliary copy variables and demonstrate a fully on-chip parallel tempering solver on an FPGA. Targeting MIMO detection, a dense, NP-hard problem central to wireless communications, we fit 15 temperature replicas of a 128-node sparsified system (1,920 p-bits) entirely on-chip and achieve bit error rates significantly below conventional linear detectors. We report complete end-to-end solution times of 4.7 ms per instance, with all loading, sampling, readout, and verification overheads included. ASIC projections in 7 nm technology indicate about 90 MHz operation with less than 200 mW power dissipation, suggesting that massive parallelism across multiple…
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Taxonomy
TopicsError Correcting Code Techniques · Low-power high-performance VLSI design · Advanced Wireless Communication Techniques
