VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing
Guanyuan Pan, Shuai Wang, Yugui Lin, Tiansheng Zhou, Pietro Li\`o, Zhenxin Zhao, Yaqi Wang

TL;DR
This paper introduces VLM-CAD, a novel workflow that combines vision language models with structural parsing and Bayesian optimization to improve analog circuit sizing through robust, explainable multimodal reasoning.
Contribution
The paper presents VLM-CAD, integrating a neuro-symbolic parser and an explainable Bayesian optimizer to enhance reasoning accuracy and reliability in engineering tasks.
Findings
Significantly improves spatial reasoning accuracy in circuit design.
Maintains physics-based explainability of decisions.
Achieves low power consumption with runtime under 66 minutes.
Abstract
Vision Language Models (VLMs) have demonstrated remarkable potential in multimodal reasoning, yet they inherently suffer from spatial blindness and logical hallucinations when interpreting densely structured engineering content, such as analog circuit schematics. To address these challenges, we propose a Vision Language Model-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing (VLM-CAD) designed for robust, step-by-step reasoning over multimodal evidence. VLM-CAD bridges the modality gap by integrating a neuro-symbolic structural parsing module, Image2Net, which transforms raw pixels into explicit topological graphs and structured JSON representations to anchor VLM interpretation in deterministic facts. To ensure the reliability required for engineering decisions, we further propose ExTuRBO, an Explainable Trust Region Bayesian Optimization method. ExTuRBO serves as…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsVLSI and FPGA Design Techniques · Low-power high-performance VLSI design · Physical Unclonable Functions (PUFs) and Hardware Security
