Neuromorphic FPGA Design for Digital Signal Processing

TL;DR

This paper explores neuromorphic computing principles applied to FPGA-based digital signal processing, demonstrating potential benefits in low latency, on-chip learning, and power efficiency through implementation of filters with neuromorphic techniques.

Contribution

It introduces a novel FPGA design integrating neuromorphic computing for DSP, showcasing implementation of FIR and IIR filters with potential advantages in latency and power consumption.

Findings

Neuromorphic FPGA filters exhibit low latency.

Neuromorphic approach enables on-chip learning.

Power efficiency is improved through event-driven processing.

Abstract

In this paper, the foundations of neuromorphic computing, spiking neural networks (SNNs) and memristors, are analyzed and discussed. Neuromorphic computing is then applied to FPGA design for digital signal processing (DSP). Finite impulse response (FIR) and infinite impulse response (IIR) filters are implemented with and without neuromorphic computing in Vivado using Verilog HDL. The results suggest that neuromorphic computing can provide low-latency and synaptic plasticity thereby enabling continuous on-chip learning. Due to their parallel and event-driven nature, neuromorphic computing can reduce power consumption by eliminating von Neumann bottlenecks and improve efficiency, but at the cost of reduced numeric precision.