Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs

TL;DR

This paper presents a timing fragility aware selective hardening method for RISCV soft processors on SRAM FPGAs, improving reliability while reducing overhead by considering routing-induced timing sensitivity.

Contribution

It introduces a novel approach that uses timing fragility metrics to guide selective hardening, addressing routing sensitivity overlooked by prior methods.

Findings

Achieves robustness comparable to full hardening with less overhead

Timing fragility correlates with routing delay vulnerability

Significantly reduces area and timing overhead in hardening

Abstract

Selective hardening is widely employed to improve the reliability of FPGA based soft processors while limiting the overhead of full redundancy. However, existing approaches primarily rely on architectural criticality or functional fault analysis, overlooking the impact of routing dependent timing sensitivity on processor robustness. This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs. Building on recent advances in in situ timing observability, the proposed approach quantifies the statistical timing sensitivity of pipeline components under controlled routing perturbations and uses this information to guide hardening decisions. Experimental results on a RISCV processor implemented on a commercial FPGA platform show that components exhibiting higher timing fragility also demonstrate increased vulnerability to routing induced delay effects. Leveraging this correlation, the proposed selective hardening strategy achieves robustness comparable to full hardening while significantly reducing area and timing overhead. These results demonstrate that timing fragility provides a practical and effective metric for reliability aware design optimization in FPGA based processor architectures.