Influence of Parallelism in Vector-Multiplication Units on Correlation Power Analysis

TL;DR

This paper examines how parallel processing in neural network hardware accelerators affects the security of side-channel attacks, providing theoretical models and FPGA validation to understand power correlation reductions.

Contribution

It introduces a theoretical framework and equations describing how parallelism impacts correlation power analysis success, validated through FPGA experiments.

Findings

Correlation decreases with increased parallelism

Equations accurately model power correlation behavior

Parallelism can reduce attack effectiveness

Abstract

The use of neural networks in edge devices is increasing, which introduces new security challenges related to the neural networks' confidentiality. As edge devices often offer physical access, attacks targeting the hardware, such as side-channel analysis, must be considered. To enhance the performance of neural network inference, hardware accelerators are commonly employed. This work investigates the influence of parallel processing within such accelerators on correlation-based side-channel attacks that exploit power consumption. The focus is on neurons that are part of the same fully-connected layer, which run parallel and simultaneously process the same input value. The theoretical impact of concurrent multiply-and-accumulate operations on overall power consumption is evaluated, as well as the success rate of correlation power analysis. Based on the observed behavior, equations are derived that describe how the correlation decreases with increasing levels of parallelism. The applicability of these equations is validated using a vector-multiplication unit implemented on an FPGA.